The present invention relates generally to memory interface circuitry and more particularly to a soft core logic circuit implemented in a programmable logic device that controls the operation of a programmable phase delay circuit.
The accuracy and reliability of data transmission between different electronic devices are important concerns in integrated circuit (IC) design. FIG. 1A illustrates a typical data transmission system 100 that involves two commonly used electronic devices, a high-performance memory device 110 and a programmable logic device (PLD) 120. To better interface with the memory device 110, the PLD 120 implements within itself a memory interface controller 130, specifically responsible for receiving/sending data from/to the memory device 110. To synchronize the operation of the memory device 110 and the controller 130, an off-chip oscillator 140 generates a reference clock signal, RefCLK, and passes it to the memory interface controller 130 and the memory device 110.
Typically, the memory device 110 and the PLD 120 are connected by multiple data groups 150. Each data group 150 includes a number of channels carrying a plurality of data signals (DQ) and one channel carrying a data strobe signal (DQS). DQS is a special signal that samples the corresponding data signals in the same data group at an electronic device's input/output (IO) interface, e.g., the memory interface controller 130. A data sampling scheme in which DQ is sampled once per DQS cycle, e.g., at its rising edge, is referred to as single-data-rate (SDR) sampling, while a data sampling scheme in which DQ is sampled multiple times per DQS cycle is called multiple-data-rate (MDR) sampling. The most common MDR sampling is the double-data-rate (DDR) sampling in which DQ is sampled twice per DQS cycle, once on the rising edge and once on the falling edge of DQS, both of which are referred to as DQS's data sampling edges.
The most significant advantage of a DDR-based device is that it doubles its IO throughput when compared with an SDR-based device operating at the same frequency. For convenience, data arriving at the PLD 120 from the memory device 110 is called “read data” and data leaving for the memory device 110 from the PLD 120 is called “write data”. Accordingly, the data strobe signal associated with the read data (or write data) is referred to as the read strobe signal (or write strobe signal).
Most memory chip standards provide that a read strobe signal be edge-aligned with a set of read data signals. In other words, there is no phase shift between the two types of signals when they leave a memory device and arrive at another device's IO interface. However, such an arrangement is not preferred for data sampling accuracy. To capture the read data signals accurately, it is preferred that the edge of the read strobe signal arrive after the edge of the read data signals. Conventionally, a dedicated phase delay circuit, standalone from or incorporated into the memory interface controller 130, is employed to produce a desired phase shift, e.g., 90°, on the read strobe signal so that the read strobe signal is center-aligned with the read data signals.
FIG. 1B schematically illustrates a typical DDR sampling scheme that can be applied to a memory interface circuit. Initially, a strobe signal (DQS) is edge-aligned with a data signal (DQ) when they reach the interface circuit. The strobe signal is then delayed by a particular phase-shift value Φshift, so as to shift each of its data sampling edges to approximately the center of a data sampling window Wsampling associated with each data bit of the data signal and thereby prevent data sampling errors.
In reality, the read data signals and the read strobe signal are not exactly edge-aligned when they arrive at a device's IO interface due to various off-chip and on-chip skewing factors, such as routing mismatches between the read data signal and the read strobe signal, rise/fall delay mismatches between the read data signal and the read strobe signal, and power noise, etc. Therefore, a fixed phase delay, e.g., 90°, generated by the dedicated phase delay circuit may not center-align the read strobe signal with the read data signals. Meanwhile, the dedicated phase delay circuit itself usually does not have any control mechanism for its user to adjust the circuit's output. On the other hand, because of the advance of semiconductor technology, the operating frequency of a memory device keeps increasing with the result that the time period allocated to a single data bit keeps shrinking. Consequently, the dedicated 90° phase delay circuit and various data skewing factors may cause the read strobe signal to completely miss a desired data sampling window and produce errors in the sampled read data.
In general, there are two major steps in the reduction of sampling errors in the read data. The first step is to eliminate the source of each skewing factor as much as possible. For example, a careful board and package design can help to significantly reduce the routing mismatches between the read data signal and the read strobe signal. However, due to various technical reasons, it is impossible to completely remove the impact of the skewing factors. Consequently, the second step is to take into account in the determination of the phase shift in a device's IO interface design the skewing factors that cannot be eliminated.
When a chip manufacturer releases a new model of memory devices, it typically provides a device specification characterizing the primary features of the new model. The device specification also lists the maximum data skews caused by different skewing factors this new model can tolerate, which represents the worst scenario that can ever happen to this model of memory devices, even though the data skews associated with a particular memory device in a specific application are often significantly smaller than what is described in the device specification.
Not knowing the data skews in a specific application, an IC designer has to assume that reliance on the device specification is a safe bet. An inevitable side effect originating from such an assumption is that it seriously reduces the dimension of the time window associated with a group of read data signals for data sampling. On the other hand, for a read strobe signal to sample the read data signals accurately, the data sampling window associated with the read data signals has to exceed a minimum duration. As a result, the only option for the IC designer to meet the two conflicting requirements is to sacrifice the application's performance by lowering its operating frequency such that even if the data skews are considered rigidly according to the memory device's specification, there is still sufficient time for reliable data sampling.
On the other hand, the actual data skews associated with a specific memory device in a particular application are often significantly smaller than the data in the device specification and it is not necessary to restrict the IC designer to the specification if there is an approach that takes into account the actual data skews automatically.
In view of the discussion above, it is highly desirable to have a memory interface device that places the edge of a read strobe signal exactly at the center of an actual data sampling window rather than shifting it by a predetermined value (e.g., 90°). It is further desirable to implement such a device in a programmable logic device to take advantage of its flexibility.